The complexity of modern integrated circuitry (ICs) continues to increase at an dramatic rate. Modern integrated circuits include millions of transistors contained on a single substrate. In order to create the millions of transistors on the substrate, the size of each transistor has decreased dramatically. Thus, today, a single integrated circuit takes up less area, operates more quickly, and consumes less power than ever before. However, with the increase in transistor numbers on each integrated circuit, the likelihood that at least one transistor contained on the integrated circuit malfunctions after fabrication also increases. Thus, various testing methods have been developed to verify the operation of integrated circuits after fabrication but prior to sale.
One testing methodology involves providing a certain set of inputs to the integrated circuit over many clock signals, reading the outputs generated by the inputs, and comparing the outputs to expected results. When the outputs fail to correctly compare to the expected results, the integrated circuit has improperly functioned. However, in order to test each particular internal logic portion of the integrated circuit, a huge number of variations in inputs must be provided. When the output is not the correct output when designing the integrated circuit, a diagnostic engineer must still spend a huge amount of time to identify which malfunctioning transistor or set of malfunctioning transistors caused the error. Thus, in modern integrated circuits (ICs), the ability to test internal logic with standard functional or operational vectors is no longer cost efficient. The transistor-to-package pin ratio is typically too large to successfully verify the internal structure of the chip in a reasonable amount of vectors or test time.
Further, many techniques that have been used to test and verify densely packed board designs cannot be used within the operation of the IC because there is no direct access to many of the circuits within the packaged and sealed IC.
As an alternative to prior testing techniques, the test technique of internal embedded scan design has become a cost effective solution to test the operation of ICs. Scan design is accomplished by altering the structure of standard flip-flops and latches (storage elements) within the IC into scan flip-flops and latches by providing a second alternate scan input for scan data parallel to the functional data input. The alternate input for scan data is generally implemented by placing a multiplexor in front of the standard input which selects either scan data or functional data. These “scannable” elements are then connected together in a serial shift register fashion by connecting the output of one element to the scan input of a next element via a “scan chain”. The scan chain can load and unload internal IC state information by allowing scan data to be transferred from one element to another on each active clock edge when a scan enable signal is asserted.
The operation of ICs employing scan design may switch from the scan mode to the system mode at any clock cycle. In this fashion, a particular scan data sequence may be loaded into the scannable elements during scan mode, the particular sequence intending to produce a particular logic function outcome from the logic functions in the IC. Once the scan data sequence is loaded, the operation of the IC is switched to system mode for a single clock cycle, and the resulting system data is captured in the scannable elements. The IC is then placed in scan mode and clocked until the data is received at a serial output pin. The received data is then compared to expected results to verify the operation of the logic circuitry for the particular case. In this fashion, the operation of at least a portion of the logic circuitry in the IC may be verified even though this portion of the logic circuitry is internal to the IC and difficult to access directly via external pins of the IC.
By selectively loading scan data and varying clocking frequencies, the technique of providing scan data in scan mode and switching to system mode for a single clock cycle may be employed to determine the delay of portions of the logic circuitry in the IC. Scan data is first provided to the scan elements in the scan chain such that specific scan elements contain predetermined values. The predetermined values in the scan elements are selected so that specific results will be produced by the logic circuits receiving output from the scan elements and produced in connected scan elements. The predetermined values are selected so that the results produced in the connected scan elements differ from the values provided during scan mode. Thus, if the logic circuit functions properly, the data produced by the logic circuits will alter the values in the connected scan elements. However, if the logic circuits do not function within the clock period, the values in the respective scan elements will not change. Thus, by varying the scan data provided to the scan chain and also the frequency of operation, the inherent delay of particular logic circuits may be verified.
Thus, the scan design has the effect of turning each selected sequential scan device (flip-flop or latch) into an internal test point. In a typical scannable device, or for a flip-flop, the standard input is referred to as the D-input while the standard output is referred to as the Q-output. Thus, the D-input of each scannable device is a direct observable point, or primary output test point. Further, the Q-output or equivalent pin (such as Q/. an inverted output) of each scannable device becomes a direct control point, or primary input test point.
As one skilled in the art will readily appreciate, not every storage element must be converted to a scan element to provide benefits through scanning. If all elements are converted, then the design is known as a full-scan architecture. However, if only selected storage elements are converted, then the design is known as a partial-scan architecture. If either full-scan or partial-scan is supported, the economics of testing improve. A scan architecture of any type allows each scanned sequential device to be viewed as if it were a package pin which reduces the gate/transistor-to-pin ratio. Since the logic functions are more accessible, an IC incorporating scan architecture requires fewer test vectors and less test time. A reduction in testing time results in a reduction in per device cost of manufacturing the IC.
The cost of testing an IC is one of the two largest recurring economic costs in IC design, with the cost of silicon being the other. Because of the tradeoff between “cost of test” and “cost of silicon”, scan design is not universally accepted by all design organizations. The use of scan flip-flops instead of the smaller non-scanned flip-flops requires more silicon space and therefore increases the cost of silicon. Further, the routing of the scan chain adds wire connections and interconnection routing to the design that also increases silicon area.
Typically, the Q output of a register or latch is connected to the scan data input of the next register in the scan chain to form a scan network, or scan net. In the functional mode of operation these register change state, which causes toggling of data on the scan net. The scan net is never sampled in functional mode but continues to toggle because each link is connected to the Q output of active registers. This results in a waste of power due to the capacitive loading effects of the scan net.
This problem is addressed in U.S. Pat. No. 5,717,700 “Method For Creating A High Speed Scan-Interconnected Set Of Flip-Flop Elements In An Integrated Circuit To Enable Faster Scan-Based Testing.” A separate scan output is provided that includes scan enabling circuitry. This output is active only when a scan enable signal is asserted. However, a transfer gate that drives the scan output is connected directly to the Q output, so that the Q output sees an extra load that would increase the delay of the flip-flop while operating in normal mode.
U.S. Pat. No. 5,719,878 “Scannable Storage Cell And Method Of Operation” also teaches a separate enabled scan output. However, in this case a complex buffer and keeper circuit is connected to the Q output to form the separate scan output, requiring additional transistors and subsequent space.
Thus, there exists a need in the art for scan elements for a method of construction of individual scan circuits and flip-flops that facilitates the verification of an integrated circuit while allowing lower power operation in normal mode in a more spatially efficient manner.